The present invention relates to a method for designing integrated circuits which minimizes the effects of high current transients on electrostatic discharge (ESD) circuits and I/O circuits of an integrated circuit. Specifically, the method provides a heuristic method for evaluating circuit designs for their survivability prior to implementation in silicon.
As part of the process of designing integrated circuits to have a high tolerance for electrostatic discharge, and other transient current conditions which may occur on connections of an integrated circuit, each connection may be provided with an ESD protection network. The ESD network is implemented to reduce the probability of damage due to high current conditions, such as are experienced during an ESD event or electrical overstress (EOS) when the current into a circuit device may approach multiple amperes, rather than the usual operating milliampere level. These events can produce a local current, which because of the I2R effects, result in a second breakdown of a MOSFET device on the integrated circuit due to electrothermal overload. The MOSFET devices within an ESD network may under these circumstances suffer from source and drain failures, due to the thermal breakdown.
A similar result can be experienced in the driver circuits for the integrated circuit, due to abnormally high current conditions on an I/O output. It is, therefore, desirable to evaluate a circuit design, prior to implementing in silicon, and even prior to preparing the photo masks for creating the circuit in silicon.
Modern integrated circuit design is accomplished using various tools which permit the devices to be represented by shapes which are created in the photo masks. The masks create multiple levels which define the ESD devices and I/O output drivers. The present invention provides a way for checking the design of ESD networks and I/O output driver circuits to evaluate their ESD robustness from the file of data which defines the shapes of devices created by the masks for fabricating the circuit in silicon.
It is an object of this invention to provide a method for evaluating the robustness of integrated circuits.
These and other objects of the invention are provided by a method which evaluates on a level-by-level basis, the robustness of an ESD network or an I/O driver. The method incorporates various heuristic evaluations of the circuit design which, through experience, indicates the capability of the circuit to distribute power during an ESD event, or other high current event, without damage to the device.
The method provides for evaluating the degree of design symmetry of the proposed semiconductor device, by considering various topological features of the design such as the directional flow of current into and out of the device, circuit element design symmetry, contact symmetry, and other design features which reduce the robustness of an ESD protection network, or I/O output device, to transient high current conditions. The semiconductor design is checked before implementing in silicon by evaluating each ESD shape and I/O shape containing an ESD or I/O device to identify any structure which produces a nonuniform power distribution in the event of a high current condition to evaluate the robustness of the device. Each of the ESD production networks and I/O drivers planned for the device are evaluated on a level-by-level basis. In the event that any level fails the check, the level can be redesigned before implementing in silicon.